This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to static random access memory (SRAM) cells and devices.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1a. In this example, SRAM cell 12 is a conventional six-transistor (6-T) static memory cell 12, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 12 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 12 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 13a and n-channel driver transistor 14a, and the other inverter of series-connected p-channel load transistor 13b and n-channel transistor 14b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 13a, 14a constitutes storage node SNT, and the common drain node of transistors 13b, 14b constitutes storage node SNB, in this example. N-channel pass transistor 15a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass transistor 15b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass transistors 15a, 15b are driven by word line WLj for this jth row in which cell 12 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage. To access cell 12 for a read operation, word line WLj is then energized, turning on pass transistors 15a, 15b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 12 to latch in the desired state.
As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. FIG. 1b illustrates such a write failure for the case of an instance of cell 12 of FIG. 1a. In the example of FIG. 1b, SRAM cell 12 begins in the state in which storage node SNT is at a “1” and storage node SNB is at a “0”. FIG. 1b illustrates the writing of a “0” state to storage node SNT. This write is attempted by bit line BLTk being pulled low (not shown in FIG. 1b), and connected to storage node SNT by pass transistor 15a, while the precharged (Vdda) voltage is applied to storage node SNB via pass transistor 15b. The write of cell 12 thus depends on the ability of pass transistor 15a to overcome the drive of transistors 13a and 14b. 
FIG. 1b illustrates the behavior of storage nodes SNT, SNB in failed cell 12 upon word line WLj being activated. In this case, device imbalances within cell 12 prevent the “flipping” of its state. This is evident by the low voltage at bit line BLTk being unable to pull storage node SNT to a logic low level low, upon word line WLj being activated; conversely, the precharged high voltage at bit line BLBk is unable to adequately charge storage node SNB. As evident from FIG. 1b, the voltages to which storage nodes SNT, SNB are driven by this write operation do not reach the trip levels of the inverters in cell 12. Upon word line WLj returning inactive low (which turns off pass transistor 15a, 15b and disconnects storage nodes SNT, SNB from bit lines BLTk, BLBk), storage node SNT latches back to a high level despite the attempted write. The write of cell 12 to a “0” state at storage node SNT has failed.
Write failures are the converse of cell stability failures—a write failure occurs if a cell is too stubborn in changing its state, while a cell stability failure occurs if a cell changes its state too easily, such as during a write to a cell in the same column. In conventional SRAM cells such as 6-T SRAM cell 12 of FIG. 1a, the designer is faced with a tradeoff between cell stability on one hand, and write margin on the other. In a general sense, cell stability is favored by pass transistors 15a, 15b having relatively weak drive as compared with load transistors 13 and driver transistors 14, because this results in weak coupling between the bit lines and storage nodes, and relatively strong drive of the latched state at storage nodes SNT, SNB. Conversely, write margin is favored by pass transistors 15a, 15b having relatively strong drive as compared with load transistors 13 and driver transistors 14, because this enables strong coupling between the bit lines and storage nodes, resulting in storage nodes SNT, SNB having weak resistance to changing state. Accordingly, the design of conventional 6-T SRAM cells 12 involves a tradeoff between these two vulnerabilities.
Unfortunately, the design window in which both adequate cell stability and adequate write margin can be attained is becoming smaller with continued scaling-down of device feature sizes, for the reasons mentioned above. In addition, it has been observed that the relative drive capability of p-channel MOS transistors relative to re-channel MOS transistors is increasing as device feature sizes continue to shrink, which skews the design window toward cell stability over write margin.
One conventional approach toward relaxing these ever-tightening design constraints is known in the art as “write-assist”. According to this approach, the power supply bias applied to SRAM cells (e.g., power supply voltage Vdda of FIG. 1) in write cycles is reduced, or disconnected so as to float. Conventional write-assist circuitry includes a power switch associated with each column of an array, or in some cases associated with multiple columns. Floating write assist bias in write cycles is attained by the power switch disconnecting cells in the selected column from the power supply voltage. In one approach, reduced voltage write assist bias turns off, in write cycles, a power switch that is connected in parallel with a diode-connected transistor between the memory cells and the power supply voltage. The cell bias in the selected column is thus at least a diode voltage drop from the full power supply voltage, during write cycles. For either reduced or floating write assist bias, the drive of the load and driver transistors in the SRAM cell is reduced relative to the drive of the pass transistors, making it easier for the low level bit line to flip the state of the addressed cell.
As mentioned above, conventional write-assist circuitry is generally implemented on a per-column basis, in that the reduced or floating write bias is applied to one or more columns of memory cells, even though only one cell in a given column is selected for connection to the bit lines. Those cells that are “half-selected” in a write operation (i.e., are in a selected column receiving the reduced or floating write assist bias, but are not in the selected row) are vulnerable to undesired changes of state, because of the reduced cell bias. Given the large number of memory cells in a typical SRAM array, one or more retention “tail bits” with substantially weaker stability margin are often present within the array, especially in cutting-edge memories constructed with minimum feature size geometries, as mentioned above. These marginal retention tail bits require a higher cell bias in order to retain a data state during a write to a cell in the same column. As such, to avoid data retention failure, the write assist voltage must be kept above the retention voltage of the weakest, or most unstable, bits in the SRAM array. This reduces the ability of write assist techniques to widen the ever-shrinking design window.
By way of further background, my copending and commonly assigned U.S. patent application Ser. No. 12/827,706, filed Jun. 24, 2010, entitled “Bit-by-Bit Write Assist for Solid-State Memory”, describes a solid-state memory in which write assist circuitry is implemented within each memory cell. As described in this application, each memory cell includes a pair of power switch transistors that selectably apply bias (either power supply voltage Vdd or ground) to the inverters of the memory cell. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter. With bias removed from the inverters, the writing of an opposite cell state is facilitated.